Fabrication of a semiconductor device and an integrated circuit thereof begins with a semiconductor substrate and employs film formation, ion implantation, photolithographic, etching and deposition techniques to form various structural features in or on a semiconductor substrate to attain individual circuit components which are then interconnected to ultimately form an integrated semiconductor device. Escalating requirements for high densification and performance associated with ultra large-scale integration (ULSI) semiconductor devices requires smaller design features, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. As the devices and features shrink, and as the drive for higher performing devices escalates, new problems are discovered that require new methods of fabrication or new arrangements or both.
There is a demand for large-scale and ultra large-scale integration devices employing high performance metal-oxide-semiconductor (MOS) devices. MOS devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate and a channel region separating the source/drain regions. Above the channel region is typically a thin gate oxide and a conductive gate comprising conductive polysilicon or another conductive material. In a typical integrated circuit, a plurality of MOS devices of different conductivity types, such as n-type and p-type, and complementary MOS (CMOS) devices employing both p-channel and n-channel devices are formed on a common substrate. MOS technology offers advantages of significantly reduced power density and dissipation as well as reliability, circuit performance and cost advantages.
FIG. 1 illustrates a cross-sectional portion of an exemplary CMOS structure comprising a doped semiconductor substrate 10 typically of monocrystalline silicon of a first conductivity type (p or n). The CMOS structure further comprises field oxide area 12, gate oxide layer 14, conductive gate electrodes 16 and 18, typically of polysilicon, formed over gate oxide layer 14, and stepped source and drain regions 20 and 22 which include lightly or moderately doped shallow extensions 20A and 22A. Completing the MOS transistor precursor structure are insulative sidewall spacers 24A through 24D, formed on the side surfaces of each of gate electrodes 16 and 18.
The drive towards increased miniaturization and the resultant limits of conventional gate oxide layers have served as an impetus for the development of newer, high dielectric constant materials as substitutes for conventional silicon oxide-based gate oxide layers. Since the drain current in a MOS device is inversely proportional to the gate oxide thickness, the gate oxide is typically made as thin as possible commensurate with the material's breakdown potential and reliability.
Decreasing the thickness of the gate oxide layer between the gate electrode and the source/drain extension regions together with the relatively high electric field across the gate oxide layer, can undesirably cause charge carriers to tunnel across the gate oxide layer. This renders the transistor "leaky", degrading its performance. To alleviate this problem, high-k dielectrics (dielectrics that have high dielectric constants) are used as the gate insulator.
It is further desirable that the high dielectric material adheres to the intended adjacent surfaces and has relatively smooth surfaces. Another consideration is that such dielectric materials used should preferably have a high dielectric constant, as compared to the value of 4.1 to 3.9 for a conventionally employed silicon dioxide (SiO.sub.2) layer.
Hence, it would be highly advantageous to develop a process that would permit the use of optimum materials in the formation of the gate electrode structure. It would also be highly advantageous to develop methodologies capable of optimum MOS transistor formation. Accordingly, there exists a need for a method of manufacturing MOS semiconductor devices with a high dielectric gate dielectric layer that improves device performance.